Microprocessors commonly employ an internal memory control unit ("MCU") to control accesses to cache and external memory. The central processing unit ("CPU") of the microprocessor issues memory access commands to the MCU. The MCU responds by performing the requested operation, and returning the requested data, if any, to the CPU.
For certain types of operations such as memory reads, the CPU must WAIT for a variable number of clock cycles before the MCU completes the requested operation and returns the requested data to the CPU. Handshaking is therefore required to signal to the CPU that the requested operation is complete, and/or that the requested data is being driven on an internal bus between the MCU and CPU during the current clock cycle.
During the variable time period in which the CPU waits for the MCU to retrieve and return the requested data, it is necessary to preserve the status of some or all of the registers internal to the CPU. These registers are typically comprise flip-flops that are clocked by a CPU clock. Unless each flip-flop is effectively disabled during clock cycles for which the CPU waits for the MCU to complete the requested operation, data will be clocked through the flip-flops and CPU register values will change.
Microprocessors such as the 486 preserve the status of the CPU registers by using a WAIT signal generated by the MCU. During clock cycles for which the WAIT signal is asserted by the MCU, or "wait states," the data values held by individual CPU flip-flops are circulated. Data circulation is accomplished by using a multiplexer to select a feedback path to connect the data output of each flip-flop to its respective input. This effectively disables the CPU registers by preventing the data values held by the CPU flip-flops from changing.
One problem with this approach results from the need to run enable signals to each of the numerous flip-flops within the CPU, and from the need to include extra logic to circulate the data held by each flip-flop. An additional problem results from the need to account for skew between the clock signal and enable signal at each flip-flop location. The design of the CPU would therefore be significantly simplified if the enable signal lines and circulation logic associated with each flip-flop were eliminated.